1. Field of the Invention
This invention relates to a discretionary process for interconnecting semiconductor devices formed on a single wafer and, more particularly, to an additive process which differentiates acceptable devices from unacceptable devices on the wafer and permits only the acceptable devices to be interconnected.
2. Description of the Prior Art
In "Active Memory Calls for Discretion", by Canning et al., Electronics, Feb. 20, 1967, pp. 143 to 154, a discretionary wiring approach which assures high yield in 1600-bit memory slices is disclosed. In discretionary wiring, each cell is tested prior to interconnection, and only the "good" or acceptable circuits are used in the final array. "Good" and "bad" (i.e., unacceptable) cells on the slice are determined by an automatically stepped multipoint probe controlled by a computer. This test information is stored on tape for later processing by a high speed central computer. A unique discretionary interconnection pattern is determined by the computer utilizing the test data. The pattern bypasses defective cells on the slice. The pattern is input into a multilevel interconnection generator (MIG) in which a computer controlled cathode ray tube beam generates the required pattern on film forming a mask. The mask is then used to form the interconnection pattern.
U.S. Pat. No. 3,702,025 to Archer discloses a simplified discretionary interconnection process wherein numerous identical or similar cells are formed into a continuous chain of such cells on a single semiconductor wafer. The cells are catalogued as either "good" or "bad" cells using a test probe and recording means. The cells are then covered with a dielectric layer and a second layer connection pattern is formed. Connections are made to contacts on the "good" cells only with the connection pattern skipping across defective cells. The invention is not usable where there is no systematic connection of chains of cells.
In the cross-referenced patent application, a plurality of substantially identical semiconductor devices are formed on a single wafer. The devices are individually tested and categorized as acceptable or unacceptable depending on preselected parameters. Only the acceptable devices are coupled together in parallel to form a parallel array. This is accomplished by a process which involved overcoating the device contact with a suitable insulating coating, such as two spin-coated dielectric layers, selectively forming openings through the insulating coating using laser drilling to the pads of the acceptable devices, and depositing a metallization layer over the coating and through the openings to contact the pads of acceptable devices. The metallization layer is then patterned to form separate conductive runs, one for each set of similar contact pads on the devices, each set of contact pads corresponding to a different active semiconductor region of each device. A preselected number of arrays are coupled in parallel to form a mosaic having the desired power rating. The cross-referenced application relates to a subtractive process in that an overlying layer of polyimide is ablated with a laser where a contact via is to be formed for interconnection of active cells.
The prior art does not teach an additive process for fabricating large power semiconductor chips. Subtractive processes require more vias to be serviced than additive processes in that the majority of devices on a wafer are acceptable, and therefore laser drilling is required to form vias to the contact pads of a majority of devices.